With rapid development of data communication and the Internet, a network point-to-point application, an online application, and a video service are increasing exponentially. Massive digital media content promotes a dramatic tenfold or hundredfold increase in Internet traffic. Currently, a system whose transmission rate is 100000 megabits per second (that is, 100 Gbps) is commercially used by operators. A 400 G system can further improve a network capacity and reduce transmission costs per bit on a basis of 100 G, so as to effectively relieve pressure of continuously increasing service traffic and network bandwidth on operators.
In a 100 G system, a quadrature phase shift keying (QPSK) modulation technology, a coherent detection technology, and a digital signal processing (DSP) technology are used to reduce an optical signal-to-noise ratio (OSNR) capacity of the system to an order of magnitude of 10 G, so that a requirement of the system for an optical fiber is lowered.
Problems such as OSNR limitation, noise, and non-linearity in the 400 G system limit a transmission distance. Currently, a transmission distance of the 400 G system in which a mainstream device uses dual carriers and a quadrature amplitude modulation (16 QAM) technology is about only one third of that of the 100 G system. Therefore, requirements for a system capacity and a transmission distance need to be comprehensively considered for high-rate system construction.
In the prior art, QPSK and polarization division multiplexing-quadrature phase shift keying (PDM-QPSK) are implemented based on a lithium niobate (LiNbO3) device. Referring to FIG. 1, FIG. 1 is a schematic architecture diagram in which QPSK and PDM-QPSK are implemented in the prior art. A sinusoidal modulation curve may be obtained by using this modulation architecture.
However, because the modulation curve is a sinusoidal curve, during higher order modulation such as 16 QAM, a digital to analog converter (DAC) is required to perform non-linear compensation. Consequently, compensation power consumption and a chip scale of a digital signal processor (DSP) are increased, and in particular, more compensation power consumption and a larger chip scale are required during higher order modulation.